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Margus Roo –

If you're inventing and pioneering, you have to be willing to be misunderstood for long periods of time

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Full adder in Basys2 in VHDL

Posted on March 21, 2016 by margusja

Plan – and truth table

2016-03-21 22.14.43

Code in github – https://github.com/margusja/FullAdder

And some pics

a is on, result sum is on

2016-03-21 20.22.19
b is on, result sum is on
2016-03-21 20.22.56
a, b, overflow are on, result sum on and output overflow is on
2016-03-21 22.14.30

Posted in Elektroonika

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Basys2 – 30bit counter with leds
Apache-Flink on my machine

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